1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor IC (integrated circuit) including a bipolar transistor and a resistor, and particularly to an accurate control of a current amplification factor h.sub.FE of the bipolar transistor.
2. Description of the Prior Art
Generally, a bipolar semiconductor IC comprises a vertical npn transistor. In forming the npn transistor, a base region is formed by impurity diffusion in a surface layer of a collector region and an emitter region is formed by impurity diffusion in a surface layer of the base region. Thus, in fabrication of the bipolar type semiconductor IC, the steps of forming the base and emitter regions by diffusion are indispensable fundamental steps of fabrication. In addition, the step of forming buried layers of a high impurity concentration for decreasing electrical resistance of the collector, the step of growing an epitaxial layer, the step of forming junction isolation regions for isolating circuit elements, and the step of forming electrodes for electrical connection are also fundamental steps indispensable for fabrication of the bipolar semiconductor IC.
On the other hand, in a bipolar semiconductor IC, it is often necessary to form, other than the npn transistor, a pnp transistor, a resistor, a capacitor, a Zener diode and the like on the same substrate. In order to avoid complexity of fabrication processes, it is desirable to form such circuit elements concurrently in any of the above described fundamental steps as far as possible. However, since the conditions of the above described fundamental fabrication steps are selected to obtain optimum characteristics of the npn transistor, it is often difficult to incorporate other circuit elements concurrently by using only the fundamental fabrication steps. Accordingly, new steps other than the above described fundamental fabrication steps are sometimes adopted to form other circuit elements than the npn transistor or to improve characteristics of such circuit elements.
Such additional steps are for example as follows: a p.sup.+ diffusion step of forming an anode region in addition to the cathode region of the Zener diode formed concurrently in the same step as the diffusion step of forming the emitter of the npn transistor, a diffusion step or an ion implantation step of forming a resistor region having a specific resistance different from that of the base region of the npn transistor, a step of forming a nitride layer as a dielectric layer of a capacitor having a capacitance larger than that of a MOS (metal oxide semiconductor) capacitor, and a step of forming a collector region of low resistance for lowering the collector resistance of the npn transistor. Those additional steps are optional steps to be adopted in view of the applications or purposes for which the bipolar IC is used or the manufacturing cost thereof.
Referring to FIG. 1, there is shown a schematic sectional view of a semiconductor IC including a vertical npn transistor and a resistor formed by using some of the above described optional steps. Buried layer 2 of n.sup.+ type are formed on a p type semiconductor substrate 1. The substrate 1 and the buried layers 2 are covered with an n type epitaxial layer 3. The epitaxial layer 3 is divided into islands 5 as regions for forming circuit elements, by p.sup.+ type isolation regions 4. A base region 6, an emitter region 7 and a collector contact region 8 of an npn transistor are formed in a surface layer of an island 5. A resistor region 9 and contact regions 10 are formed in a surface layer of another island 5. The resistor region 9 is formed by ion implantation after the base region 6 has been formed by diffusion.
The semiconductor IC as shown in FIG. 1 is described for example in Japanese Patent Publication No. 2182/1982.
However, when the resistor region 9 formed by ion implantation is annealed, the impurity in the base region 6 is unavoidably diffused to a certain extent. Accordingly, it is difficult to accurately control a current amplification factor h.sub.FE of the npn transistor.
In addition, it is necessary to change heat treatment conditions for forming the base region dependently on whether the optional step of forming the resistor 9 by ion implantation is adopted or not. In other words, it is also necessary to change conditions in the above described fundamental steps for a semiconductor IC to be fabricated by using optional steps.